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rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. ad7712 * lc 2 mos signal conditioning adc functional block diagram clock generation serial interface output register charge-balancing a/d converter auto-zeroed modulator digital filter ad7712 agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(? ref in (? ref in (+) sync 4.5 a a = 1 ?128 drdy tfs rfs ref out v bias voltage attenuation ain2 tp standby control register v ss 2.5v reference dv dd av dd av dd m u x ain1(+) pga features charge balancing adc 24 bits no missing codes 0.0015% nonlinearity high level and low level analog input channels programmable gain for both inputs gains from 1 to 128 differential input for low level channel low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients bidirectional microcontroller serial interface internal/external reference option single- or dual-supply operation low power (25 mw typ) with power-down mode (100 w typ) applications process control smart transmitters portable industrial instruments general description the ad7712 is a complete analog front end for low frequency measurement applications. the device has two analog input channels and accepts either low level signals directly from a trans- ducer or high level ( 4 v ref ) signals, and outputs a serial digital word. it employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. the low level input signal is applied to a proprietary programmable gain front end based around an analog modulator. the high level analog input is attenuated before being applied to the same modulator. the modulator output is processed by an on-chip digital filter. the first notch of this digital filter can be programmed via the on-chip control register, allowing adjustment of the filter cutoff and settling time. normally, one of the channels will be used as the main channel with the second channel used as an auxiliary input to periodi- cally measure a second voltage. the part can be operated from a single supply (by tying the v ss pin to agnd), provided that the input signals on the low level analog input are more positive than ?0 mv. by taking the v ss pin negative, the part can con- vert signals down to ? ref on this low level input. this low level input, as well as the reference input, features differential input capability. the ad7712 is ideal for use in smart, microcontroller based systems. input channel selection, gain settings, and signal polar- ity can be configured in software using the bidirectional serial port. the ad7712 also contains self-calibration, system calibra- tion, and background calibration options, and allows the user to read and to write the on-chip calibration registers. cmos construction ensures low power dissipation, and a hard- ware programmable power-down mode reduces the standby power consumption to only 100 w typical. the part is available in a 24-lead, 0.3 inch wide, plastic and hermetic dual-in-line pack- age (dip), as well as a 24-lead small outline (soic) package. product highlights 1. the low level analog input channel allows the ad7712 to accept input signals directly from a strain gage or transducer, removing a considerable amount of signal conditioning. to maximize the flexibility of the part, the high level analog input accepts signals of 4 v ref /gain. 2. the ad7712 is ideal for microcontroller or dsp processor applications with an on-chip control register that allows control over filter cutoff, input gain, channel selection, signal polarity, and calibration modes. 3. the ad7712 allows the user to read and to write the on-chip calibration registers. this means that the microcontroller has much greater control over the calibration procedure. 4. no missing codes ensures true, usable, 23-bit dynamic range coupled with excellent 0.0015% accuracy. the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. * protected by u.s. patent no. 5,134,401.
rev. f e2e ad7712especifications parameter a, s versions 1 unit conditions/comments static performance no missing codes 24 bits min guaranteed by design. for filter notches 60 hz 22 bits min for filter notch = 100 hz 18 bits min for filter notch = 250 hz 15 bits min for filter notch = 500 hz 12 bits min for filter notch = 1 khz output noise see tables i and ii depends on filter cutoffs and selected gain integral nonlinearity @ 25 c 0.0015 % fsr max filter notches 60 hz t min to t max 0.003 % fsr max typically 0.0003% positive full-scale error 2, 3, 4 excluding reference full-scale drift 5 1 v/ c typ excluding reference. for gains of 1, 2 0.3 v/ c typ excluding reference. for gains of 4, 8, 16, 32, 64, 128 unipolar offset error 2, 4 unipolar offset drift 5 0.5 v/ c typ for gains of 1, 2 0.25 v/ c typ for gains of 4, 8, 16, 32, 64, 128 bipolar zero error 2, 4 bipolar zero drift 5 0.5 v/ c typ for gains of 1, 2 0.25 v/ c typ for gains of 4, 8, 16, 32, 64, 128 gain drift 2 ppm/ c typ bipolar negative full-scale error 2 @ 25 c 0.003 % fsr max excluding reference t min to t max 0.006 % fsr max typically 0.0006% bipolar negative full-scale drift 5 1 v/ c typ excluding reference. for gains of 1, 2 0.3 v/ c typ excluding reference. for gains of 4, 8, 16, 32, 64, 128 analog inputs/reference inputs normal-mode 50 hz rejection 6 100 db min for filter notches of 10 hz, 25 hz, 50 hz, 0.02 f notch normal-mode 60 hz rejection 6 100 db min for filter notches of 10 hz, 30 hz, 60 hz, 0.02 f notch ain1/ref in dc input leakage current @ 25 c 6 10 pa max t min to t max 1 na max sampling capacitance 6 20 pf max common-mode rejection (cmr) 100 db min at dc and av dd = 5 v 90 db min at dc and av dd = 10 v common-mode 50 hz rejection 6 150 db min for filter notches of 10 hz, 25 hz, 50 hz, 0.02 f notch common-mode 60 hz rejection 6 150 db min for filter notches of 10 hz, 30 hz, 60 hz, 0.02 f notch common-mode voltage range 7 v ss to av dd v min to v max analog inputs 8 input sampling rate, f s see table iii ain1 input voltage range 9 for normal operation. depends on gain selected 0 v to v ref 10 v max unipolar input range (b/u bit of control register = 1) v ref v max bipolar input range (b/u bit of control register = 0) ain2 input voltage range 9 for normal operation. depends on gain selected 0 v to 4 v ref 10 v max unipolar input range (b/u bit of control register = 1) 4 v ref v max bipolar input range (b/u bit of control register = 0) ain2 dc input impedance 30 k ain2 gain error 11 0.05 % typ additional error contributed by resistor attenuator ain2 gain drift 1 ppm/ c typ additional drift contributed by resistor attenuator ain2 offset error 11 10 mv max additional error contributed by resistor attenuator ain2 offset drift 20 v/ c typ reference inputs ref in(+) e ref in(e) voltage 12 2.5 to 5 v min to v max for specified performance. part is functional with lower v ref voltages input sampling rate, f s f clk in /256 notes 1 temperature range is as follows: a version, e40 c to +85 c; s version e55 c to +125 c. see also note 18. 2 applies after calibration at the temperature of interest. 3 positive full-scale error applies to both unipolar and bipolar input ranges. 4 these errors will be of the order of the output noise of the part as shown in table i after system calibration. these errors wi ll be 20 v typical after self-calibration or background calibration. 5 recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 these numbers are guaranteed by design and/or characterization. 7 this common-mode voltage range is allowed, provided that the input voltage on ain1(+) and ain1(e) does not exceed av dd + 30 mv and v ss e 30 mv. 8 the ain1 analog input presents a very high impedance dynamic load that varies with clock frequency and input sample rate. the m aximum recommended source resistance depends on the selected gain (see tables iv and v). 9 the analog input voltage range on the ain1(+) input is given here with respect to the voltage on the ain1(e) input. the input v oltage range on the ain2 input is with respect to agnd. the absolute voltage on the ain1 input should not go more positive than av dd + 30 mv or more negative than v ss e 30 mv. 10 v ref = ref in(+) e ref in(e). 11 this error can be removed using the system calibration capabilities of the ad7712. this error is not removed by the ad7712?s se lf-calibration features. the offset drift on the ain2 input is 4 times the value given in the static performance section. 12 the reference input voltage range may be restricted by the input voltage range requirement on the v bias input. (av dd = +5 v 5%; dv dd = +5 v 5%; v ss = 0 v or e5 v 5%; ref in(+) = +2.5 v; ref in(e) = agnd; mclk in = 10 mhz unless otherwise stated. all specifications t min to t max , unless otherwise noted.)
rev. f ad7712 e3e specifications (continued) parameter a, s versions 1 unit conditions/comments reference output output voltage 2.5 v nom initial tolerance 1% max drift 20 ppm/ c typ output noise 30 v typ pk-pk noise; 0.1 hz to 10 hz bandwidth line regulation (av dd )1 mv/v max load regulation 1.5 mv/ma max maximum load current 1 ma external current 1 ma max v bias input 13 input voltage range av dd e 0.85 v ref see v bias input section or av dd e 3.5 v max whichever is smaller: +5 v/e5 v or +10 v/0 v nominal av dd /v ss or av dd e 2.1 v max whichever is smaller: +5 v/0 v nominal av dd /v ss v ss + 0.85 v ref see v bias input section or v ss + 3 v min whichever is greater: +5 v/e5 v or +10 v/0 v nominal av dd /v ss or v ss + 2.1 v min whichever is greater: +5 v/0 v nominal av dd /v ss v bias rejection 65 to 85 db typ increasing with gain logic inputs input current 10 a max all inputs except mclk in v inl , input low voltage 0.8 v max v inh , input high voltage 2.0 v min mclk in only v inl , input low voltage 0.8 v max v inh , input high voltage 3.5 v min logic outputs v ol , output low voltage 0.4 v max i sink = 1.6 ma v oh , output high voltage 4.0 v min i source = 100 a floating state leakage current 10 a max floating state output capacitance 14 9 pf typ transducer burnout current 4.5 a nom initial tolerance 10 % typ drift 0.1 %/ c typ system calibration ain1 positive full-scale calibration limit 15 (1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) negative full-scale calibration limit 15 e(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limit 16, 17 e(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) input span 15 0.8 v ref /gain v min gain is the selected pga gain (between 1 and 128) (2.1 v ref )/gain v max gain is the selected pga gain (between 1 and 128) ain2 positive full-scale calibration limit 15 (4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) negative full-scale calibration limit 15 e(4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limit 17 e(4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) input span 15 3.2 v ref /gain v min gain is the selected pga gain (between 1 and 128) (8.4 v ref )/gain v max gain is the selected pga gain (between 1 and 128) notes 13 the ad7712 is tested with the following v bias voltages. with av dd = 5 v and v ss = 0 v, v bias = 2.5 v; with av dd = 10 v and v ss = 0 v, v bias = 5 v and with av dd = 5 v and v ss = e5 v, v bias = 0 v. 14 guaranteed by design, not production tested. 15 after calibration, if the analog input exceeds positive full scale, the converter will output all 1s. if the analog input is le ss than negative full scale, then the device will output all 0s. 16 these calibration and span limits apply provided the absolute voltage on the ain1 analog inputs does not exceed av dd + 30 mv or does not go more negative than v ss e 30 mv. 17 the offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
rev. f e4e ad7712especifications caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7712 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. parameter a, s versions 1 unit conditions/comments power requirements power supply voltages av dd voltage 18 +5 to +10 v nom 5% for specified performance dv dd voltage 19 +5 v nom 5% for specified performance av dd e v ss voltage +10.5 v max for specified performance power supply currents av dd current 4 ma max dv dd current 4.5 ma max v ss current 1.5 ma max v ss = e5 v power supply rejection 20 rejection w.r.t. agnd; assumes v bias is fixed positive supply (av dd and dv dd ) 21 db typ negative supply (v ss )90 db typ power dissipation normal mode 45 mw max av dd = dv dd = +5 v, v ss = 0 v; typically 25 mw normal mode 52.5 mw max av dd = dv dd = +5 v, v ss = e5 v; typically 30 mw standby (power-down) mode 22 200 w max av dd = dv dd = +5 v, v ss = 0 v or e5 v; typically 100 w notes 18 the ad7712 is specified with a 10 mhz clock for av dd voltages of +5 v 5%. it is specified with an 8 mhz clock for av dd voltages greater than 5.25 v and less than 10.5 v. operating with av dd voltages in the range 5.25 v to 10.5 v is guaranteed only over the 0 c to 70 c temperature range. 19 the 5% tolerance on the dv dd input is allowed provided that dv dd does not exceed av dd by more than 0.3 v. 20 measured at dc and applies in the selected passband. psrr at 50 hz will exceed 120 db with filter notches of 10 hz, 25 hz, or 5 0 hz. psrr at 60 hz will exceed 120 db with filter notches of 10 hz, 30 hz, or 60 hz. 21 psrr depends on gain: gain of 1 = 70 db typ; gain of 2 = 75 db typ; gain of 4 = 80 db typ; gains of 8 to 128 = 85 db typ. these numbers can be improved (to 95 db typ) by deriving the v bias voltage (via zener diode or reference) from the av dd supply. 22 using the hardware standby pin. standby power dissipation using the software standby bit (pd) of the control register is 8 mw t yp. specifications subject to change without notice. absolute maximum ratings * (t a = 25 c, unless otherwise noted.) av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v av dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +12 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to e6 v v ss to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to e6 v ain1 input voltage to agnd . . . v ss e 0.3 v to av dd + 0.3 v reference input voltage to agnd . . v ss e 0.3 v to av dd + 0.3 v ref out to agnd . . . . . . . . . . . . . . . . . . . . e0.3 v to av dd ordering guide model temperature range package options * ad7712an e40 c to +85 c n-24 ad7712ar e40 c to +85 c rw-24 ad7712ar-reel e40 c to +85 c rw-24 ad7712ar-reel7 e40 c to +85 c rw-24 ad7712aq e40 c to +85 c q-24 ad7712sq e55 c to +125 c q-24 eval-ad7712eb evaluation board * n = pdip, q = cerdip; rw = soic. digital input voltage to dgnd . . . . . e0.3 v to av dd + 0.3 v digital output voltage to dgnd . . . . e0.3 v to dv dd + 0.3 v operating temperature range commercial (a version) . . . . . . . . . . . . . . . e40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . e55 c to +125 c storage temperature range . . . . . . . . . . . . . e65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . . 300 c power dissipation (any package) to 75 c . . . . . . . . . . 450 mw * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
rev. f ad7712 e5e limit at t min , t max parameter (a, s versions) unit conditions/comments f clk in 4, 5 master clock frequency: crystal oscillator or externally supplied 400 khz min av dd = 5 v 5% 10 mhz max for specified performance 8 mhz av dd = 5.25 v to 10.5 v t clk in lo 0.4 t clk in ns min master clock input low time; t clk in = 1/f clk in t clk in hi 0.4 t clk in ns min master clock input high time t r 6 50 ns max digital output rise time; typically 20 ns t f 6 50 ns max digital output fall time; typically 20 ns t 1 1000 ns min sync sc 2 drdy rfs st cin cin drdy rfs t 2 cin a rfs st a rfs t cin 2 rfs scf cin 2 dat rfs d cin 2 scfdd cin 2 cin 2 sc cin 2 sc a tfs st a tfs t cin 2 tfs scfdt cin tfs scft dscst dsct nts s a 2 sf tad2a dd ia dd 2 cincinad2standbyi tad2 cin a dd 2i s tf 2 d dd a dd ss anddnd cin id dd tiincaractristics 2
rev. f e6e ad7712 limit at t min , t max parameter (a, s versions) unit conditions/comments external clocking mode f sclk f clk in /5 mhz max serial clock input frequency t 20 0 ns min drdy rfs st 2 drdy rfs t 22 2 cin a rfs st 2 a rfs t 2 cin dat rfs d 2 scfdd 2 cin 2 2 2 cin sc 2 2 cin sc 2 cin scf drdy 2 scdt cin rfs tfs scft cin 2 rfs dt 2 a tfs st a tfs t cin scf tfs t 2 cin sc dscst dsct nts tf t ft s ttt in 2 a 2 a f f cat brt incnfiratin disic ti ns 2 2 22 2 2 2 2 ad2 a dd ss t standby ain cin ct a ain d sc sync bias rfin rfin rft ain2 dnd d dd sdata drdy and tfs rfs tiincaractristics
rev. f ad7712 e7e pin function description pin mnemonic function 1 sclk serial clock. logic input/output, depending on the status of the mode pin. when mode is high, the device is in its self-clocking mode, and the sclk pin provides a serial clock output. this sclk becomes active when rfs tfs rfs tfs d sct a ad2 2 cin c sdta cinctacin csctt ct cinct a a i sync iaad2i d i ain aictain t ain aicn standby it t td ss anstandtain ss 2 a dd as bias ibt bias rf a dd bias rf ss rf rfinrfinia dd ss ta dd ss rfta dd ss anda dd rfin ritrfina dd ss rfin rfin rfin ritrfinrfin rfina dd ss rft rt2t and ain2 aic2 rf aina rf 2ain2 and rac tfs tfsa i tfs i tfs 2 rfs rfsai scsdata rfs i sdata rfs
rev. f e8e ad7712 pin mnemonic function 21 drdy at drdy drdy ad2 22 sdata sdi d rfs drdy dsc tfs t 2 d dd dsd dd a dd 2 dnd rdc triny in t t sb sb t fs fain ain rf ain2sbain2 rf ain2sb fain ainsbain2sb b t fain ain sbain2 sb bnfs t fainain rf ainsbain2 rf ainsb fs ain ain rf ainain2 rf ain nfs t ainain rf ainain2 rf ain n ain ain ain ss cr iad2 t ad2 fscr tad2 is i ad2 t ad2
rev. f ad7712 e9e control register (24 bits) a write to the device with the a0 input low writes data to the control register. a read to the device with the a0 input low acc esses the contents of the control register. the control register is 24 bits wide and when writing to the register 24 bits of data must be written otherwise the data will not be loaded to the control register. in other words, it is not possible to write just the first 12 bi ts of data into the control register. if more than 24 clock pulses are provided before tfs 2 s2 sb d2 d d 2 c d b b fs fs fs fs fs fs fs fs fs fs2 fs fs dc sb d2 d d nt t asctct d2dd t drdy f rf asctct drdy t asct drdy asct ct drdy f rf abctci ad2 t i i rf rsccaa caa ct 2 t2 rfsccaa caa ct 2 t2
rev. f e10e ad7712 pga gain g2 gl g0 gain 00 01 (default condition after the internal power-on reset) 00 1 2 01 0 4 01 1 8 10 0 16 10 1 32 11 0 64 11 1 128 channel selection ch channel 0a in 1l ow level input (default condition after the internal power-on reset) 1 ain2 high level input power-down pd 0n ormal operation (default condition after the internal power-on reset) 1 power-down word length wl output word length 0 16-bit (d efault condition after internal power-on reset) 1 24-bit burnout current bo 0o ff (default condition after internal power-on reset) 1on bipolar/unipolar selection (both inputs) b/u 0 bipolar (default condition after internal power-on reset) 1 unipolar filter selection (fs11efs0) the on-chip digital filter provides a sinc 3 (or (sinx/x) 3 ) filter response. the 12 bits of data programmed into these bits deter- mine the filter cutoff frequency, the position of the first notch of the filter, and the data rate for the part. in association with the gain selection, it also determines the output noise (and therefore the effective resolution) of the device. the first notch of the filter occurs at a frequency determined by the relationship filter first notch frequency = (f clk in /512)/ code where code is the decimal equivalent of the code in bits fs0 to fs11 and is in the range 19 to 2,000. with the nominal f clk in of 10 mhz, this results in a first notch frequency range from 9.76 hz to 1.028 khz. to ensure correct operation of the ad7712, the value of the code loaded to these bits must be within this range. failure to do this will result in unspecified operation of the device. changing the filter notch frequency, as well as the selected gain, impacts resolution. tables i and ii and figure 2 show the effect of the filter notch frequency and gain on the effective resolution of the ad7712. the output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. for example, if the first notch of the filter is selected at 50 hz, then a new word is available at a 50 hz rate or every 20 ms. if the first notch is at 1 khz, a new word is avail- able every 1 ms. the settling time of the filter to a full-scale step input change is worst case 4 1/(output data rate). this settling time is to 100% of the final value. for example, with the first filter notch at 50 hz, the settling time of the filter to a full-scale step input change is 80 ms max. if the first notch is at 1 khz, the settling time of the filter to a full-scale input step is 4 ms max. this settling time can be reduced to 3 l/(output data rate) by syn- chronizing the step input change to a reset of the digital filter. in other words, if the step input takes place with sync i sync tb b 22
rev. f ad7712 e11e tables i and ii show the output rms noise for some typical notch and e3 db frequencies. the numbers given are for the bipolar input ranges with a v ref of 2.5 v. these numbers are typical and are generated with an analog input voltage of 0 v. the output noise from the part comes from two sources. first, there is the electrical noise in the semiconductor devices used in the implementation of the modulator (device noise). second, when the analog input signal is converted into the digital do- main, quantization noise is added. the device noise is at a low level and is largely independent of frequency. the quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. consequently, lower filter notch settings (below 60 hz approximately) tend to be device noise dominated while higher notch settings are domi- nated by quantization noise. changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic im provement in noise performance than it does in the device noise dominated region as shown in table i. fur thermore, quantization noise is added after the pga, so effective resolution is independent of gain for the higher filter table i. output noise vs. gain and first notch frequency first notch of filter and o/p e3 db g ain of gain of gain of gain of gain of gain of gain of gain of data rate 1 frequency 1248163264128 10 hz 2 2.62 hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25 25 hz 2 6.55 hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38 30 hz 2 7.86 hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4 50 hz 2 13.1 hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46 60 hz 2 15.72 hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56 100 hz 3 26.2 hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65 250 hz 3 65.5 hz 130 75 25 12 7.5 4 2.7 1.7 500 hz 3 131 hz 0.6 10 3 0.26 10 3 140 70 35 25 15 8 1 khz 3 262 hz 3.1 10 3 1.6 10 3 0.7 10 3 0.29 10 3 180 120 70 40 notes 1 the default condition (after the internal power-on reset) for the first notch of filter is 60 hz. 2 for these filter notch frequencies, the output rms noise is primarily dominated by device noise, and, as a result, is independe nt of the value of the reference voltage. therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is increased since the output rms noise remains constant as the input full scale increases). 3 for these filter notch frequencies, the output rms noise is dominated by quantization noise, and, as a result, is proportional to the value of the reference voltage. table ii. effective resolution vs. gain and first notch frequency first notch of filter and o/p e3 db gain of gain of gain of gain of gain of gain of gain of gain of data rate frequency 1248163264128 10 hz 2.62 hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5 25 hz 6.55 hz 21.5 21 21 20 19.5 18.5 17.5 16.5 30 hz 7.86 hz 21 21 20.5 20 19.5 18.5 17.5 16.5 50 hz 13.1 hz 20 20 20 20 19 18.5 17.5 16.5 60 hz 15.72 hz 20 20 20 19.5 19 18 17 16 100 hz 26.2 hz 18.5 18.5 18.5 18.5 18 17.5 17 16 250 hz 65.5 hz 15 15.5 15.5 15.5 15.5 15.5 15 14.5 500 hz 131 hz 13 13 13 13 13 12.5 12.5 12.5 1 khz 262 hz 10.5 10.5 11 11 11 10.5 10 10 * effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 v ref /gain). the above table applies for a v ref of 2.5 v and resolution numbers are rounded to the nearest 0.5 lsb. typical output rms noise ( v) effective resolution * (bits) notch frequencies. meanwhile, device noise is added in the pga and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. at the lower filter notch settings (below 60 hz), the no missing codes performance of the device is at the 24-bit level. at the higher settings, more codes will be missed until at the 1 khz notch setting; no missing codes performance is guaranteed only to the 12-bit level. however, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should be more than adequate for all applications. the effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. this does not remain constant with increasing gain or with increasing band- wi dt h. table ii is the same as table i except that the output is expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 v ref /gain, i.e., the input full scale). it is possible to do post filtering on the device to improve the output data rate for a given e3 db frequency and to further reduce the output noise (see the digital filtering section).
rev. f e12e ad7712 circuit description the ad7712 is a sigma-delta a/d converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. it contains a sigma-delta (or charge- balancing) adc, a calibration microcontroller with on-chip static ram, a clock oscillator, a digital filter, and a bidirectional serial communications port. the part contains two analog input channels, one programmable gain differential input, and one programmable gain high level single-ended input. the gain range on both inputs is from 1 to 128. for the ain1 input, this means that the input can accept unipolar signals of between 0 mv and 20 mv and 0 mv and +2.5 v or bipolar signals in the range from 20 mv to 2.5 v when the reference input voltage equals 2.5 v. the input volt- age range for the ain2 input is 4 v ref /gain and is 10 v with the nominal reference of 2.5 v and a gain of 1. the i nput signal to the selected analog input channel is continuously sampled at a rate determined by the frequency of the master clock, mclk in, and the selected gain (see table iii). a chargebalancing a/d converter (sigma-delta modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. the programmable gain func tion on the analog input is also incorporated in this sigma- delta modulator with the input sampling frequency being modified to give the higher gains. a sinc 3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the first notch fre quency of this filter. the output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. the first notch of this digital filter (and therefore its e3 db frequency) can be programmed via an on-chip control register. the programmable range for this first notch frequency is from 9.76 hz to 1.028 khz, giving a programmable range for the e3 db frequency of 2.58 hz to 269 hz. the basic connection diagram for the part is shown in figure 3. this shows the ad7712 in the external clocking mode with both the av dd and dv dd pins of the ad7712 being driven from the analog 5 v supply. some applications will have separate supplies for both av dd and dv dd , and in some of these cases, the analog supply will exceed the 5 v digital supply (see the power supplies and grounding section). ref in(+) ref out ain1(+) ain1(e) ain2 agnd dgnd mclk in mclk out mode sclk sdata ref in(e) v bias a0 differential analog input single-ended analog input analog ground digital ground data ready transmit (write) receive (read) serial data serial clock address input 5v ad7712 10 f 0.1 f analog 5v supply av dd dv dd dv dd v ss standby sync drdy tfs rfs 0.1 f figure 3. basic connection diagram 1000 10 0.1 10 1000 10000 100 1 100 notch frequency e hz output noise e v gain of 16 gain of 32 gain of 64 gain of 128 figure 2b. plot of output noise vs. gain and notch frequency (gains of 16 to 128) 10000 100 0.1 10 1000 10000 gain of 1 gain of 2 gain of 4 gain of 8 1000 10 1 100 notch frequency e hz output noise e v figure 2a. plot of output noise vs. gain and notch frequency (gains of 1 to 8) figures 2a and 2b give information similar to that outlined in table i. in these plots, the output rms noise is shown for the f ull range of available cutoffs frequencies rather than for some typical cutoff frequencies as in tables i and ii. the numbers given in th ese plots are typical values at 25 c.
rev. f ad7712 e13e the ad7712 provides a number of calibration options that can be programmed via the on-chip control register. a calibration cycle can be initiated at any time by writing to this control regis- ter. the part can perform self-calibration using the on-chip calibration microcontroller and sram to store calibration parameters. other system components can also be included in the calibration loop to remove offset and gain errors in the input channel using the system calibration mode. another option is a background calibration mode where the part con tinuously performs self-calibration and updates the calibration coeffi- cients. once the part is in this mode, the user does not have to worry about issuing periodic calibration commands to the device or asking the device to recalibrate when there is a change in the ambient temperature or power supply voltage. the ad7712 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the device?s cali bration coefficients and also to write its own calibration coefficients to the part from prestored values in e 2 prom. this gives the microprocessor much greater control over the ad 7712?s calibration procedure. it also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in e 2 prom. the ad7712 can be operated in single-supply systems, provided that the analog input voltage on the ain1 input does not go more negative than e30 mv. for larger bipolar signals on the ain1 input, a v ss of e5 v is required by the part. for battery operation or low power systems, the ad7712 offers a standby mode (controlled by the standby tryfratin tadc fi a a a aad adac a ana ass fitr caratr diitadata dac sa diita fitr f sdadc i dact adcadc snr 2 b aadcsnrb tad2 tiiia t t tiiif2 t dac t i sadc a adcft i adc in diffrntia aifir caratr fs dac fs f bcbadc i dac t dac dacf dacfs fsa dacfs tad2 a
rev. f e14e ad7712 input sample rate the modulator sample frequency for the device remains at f clk in /512 (19.5 khz @ f clk in = 10 mhz) regardless of the selected gain. however, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and scaling the ratio of reference capacitor to input capacitor. as a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see table iii). the effective input impedance is 1/c f s where c is the input sampling capacitance and f s is the input sample rate. table iii. input sampling frequency vs. gain gain input sampling frequency (f s ) 1f clk in /256 (39 khz @ f clk in = 10 mhz) 22 f clk in /256 (78 khz @ f clk in = 10 mhz) 44 f clk in /256 (156 khz @ f clk in = 10 mhz) 88 f clk in /256 (312 khz @ f clk in = 10 mhz) 16 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 32 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 64 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 128 8 f clk in /256 (312 khz @ f clk in = 10 mhz) digital filtering the ad7712?s digital filter behaves like a similar analog filter, with a few minor differences. first, since digital filtering occurs after the a-to-d conversion process, it can remove noise injected during the conversion process. analog filtering cannot do this. on the other hand, analog filtering can remove noise superim- posed on the analog signal before it reaches the adc. digital filtering cannot do this, and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. to alleviate this problem, the ad7712 has overrange headroom built into the sigma-delta modulator and digital filter, which allows overrange excursions of 5% above the analog input range. if noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. this will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). filter characteristics the cutoff frequency of the digital filter is determined by the value loaded to bits fs0 to fs11 in the control register. at the maximum clock frequency of 10 mhz, the minimum cutoff frequency of the filter is 2.58 hz while the maximum programmable cutoff frequency is 269 hz. figure 6 shows the filter frequency response for a cutoff fre quency of 2.62 hz, which corresponds to a first filter notch frequency of 10 hz. this is a (sinx/x) 3 response (also called sinc 3 ), that provides >100 db of 50 hz and 60 hz rejection. programming a different cutoff frequency via fs0efs11 does not alter the profile of the filter response; it changes the fre- quency of the notches as outlined in the control register section. 0 e240 e180 e220 10 e200 0 e120 e160 e140 e100 e80 e60 e20 e40 60 50 40 30 20 frequency e hz gain e db figure 6. frequency response of ad7712 filter since the ad7712 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data on the output will be invalid after a step change until the settling time has elapsed. the settling time depends upon the notch frequency chosen for the filter. the output data rate equates to this filter notch frequency, and the settling time of the filter to a full-scale step input is four times the output data period. in applications using both input channels, the settling time of the filter must be allowed to elapse before data from the second channel is accessed. post filtering the on-chip modulator provides samples at a 19.5 khz output rate. the on-chip digital filter decimates these samples to pro- vide data at an output rate that corresponds to the programmed first notch frequency of the filter. since the output data rate exceeds the nyquist criterion, the output rate for a given band- width will satisfy most application requirements. however, there may be some applications that require a higher data rate for a given bandwidth and noise performance. applications that need this higher data rate will require some post filtering following the digital filter of the ad7712. for example, if the required bandwidth is 7.86 hz but the re quired update rate is 100 hz, the data can be taken from the ad7712 at the 100 hz rate giving a e3 db bandwidth of 26.2 hz. post filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 hz bandwidth level, while maintaining an output rate of 100 hz. post filtering can also be used to reduce the output noise from the device for bandwidths below 2.62 hz. at a gain of 128, the output rms noise is 250 nv. this is essentially device noise or white noise, and since the input is chopped, the noise has a flat frequency response. by reducing the bandwidth below 2.62 hz, the noise in the resultant passband can be reduced. a reduction in bandwidth by a factor of 2 results in a 2 t
rev. f ad7712 e15e antialias considerations the digital filter does not provide any rejection at integer mul- tiples of the modulator sample frequency (n 19.5 khz, where n = 1, 2, 3 . . . ). this means that there are frequency bands, f 3 db wide (f 3 db is cutoff frequency selected by fs0 to fs11), where noise passes unattenuated to the output. however, due to the ad7712?s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. in any case, because of the high oversampling ratio, a simple, rc, single-pole filter is generally sufficient to attenuate the signals in these bands on the analog input and thus provide adequate antialiasing filtering. if passive components are placed in front of the ain1 input of the ad7712, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. the dc input impedance for the ain1 input is over 1 g . the input appears as a dynamic load that varies with the clock frequency and with the selected gain (see figure 7). the input sample rate, as shown in table iii, determines the time allowed for the analog input capacitor, c in , to be charged. external impedances result in a longer charge time for this capacitor, which may result in gain errors being introduced on the analog inputs. table iv shows the allowable external resistance/capacitance values such that no gain error to the 16- bit level is introduced, while table v shows the allowable external resistance/capacitance values such that no gain error to the 20-bit level is introduced. both inputs of the differential input channels (ain1) look into similar input circuitry. r int (7k typ) c int (11.5pf typ) v bias ain switching frequency depends on f clkin and selected gain high impedance >1g figure 7. ain1 input impedance table iv. typical external series resistance that will not introduce 16-bit gain error external capacitance (pf) gain 0 50 100 500 1000 5000 1 184 k 45.3 k 27.1 k 7.3 k 4.1 k 1.1 k 2 88.6 k 22.1 k 13.2 k 3.6 k 2.0 k 560 4 41.4 k 10.6 k 6.3 k 1.7 k 970 270 8e128 17.6 k 4.8 k 2.9 k 790 440 120 table v. typical external series resistance that will not introduce 20-bit gain error external capacitance (pf) gain 0 50 100 500 1000 5000 1 145 k 34.5 k 20.4 k 5.2 k 2.8 k 700 2 70.5 k 16.9 k 10 k 2.5 k 1.4 k 350 4 31.8 k 8.0 k 4.8 k 1.2 k 670 170 8e128 13.4 k 3.6 k 2.2 k 550 300 80 the numbers in tables iv and v assume a full-scale change on the analog input. in any case, the error introduced due to longer charging times is a gain error that can be removed using the system calibration capabilities of the ad7712 provided that the resultant span is within the span limits of the system calibration techniques for the ad7712. the ain2 input contains a resistive attenuation network as outlined in figure 8. the typical input impedance on this input is 44 k . as a result, the ain2 input should be driven from a low impedance source. 33k v bias ain2 11k modulator circuit figure 8. ain2 input impedance
rev. f e16e ad7712 analog input functions analog input ranges the analog inputs on the ad7712 provide the user with consid- erable flexibility in terms of analog input voltage ranges. one of the inputs is a differential, programmable gain, input channel that can handle either unipolar or bipolar input signals. the common-mode range of this input is from v ss to av dd pro vided that the absolute value of the analog input voltage lies between v ss e 30 mv and av dd + 30 mv. the second analog input is a single-ended, programmable gain, high level input that accepts analog input ranges of 0 to +4 v ref /gain or 4 v ref / gain. the dc input leakage current on the ain1 input is 10 pa maxi- mum at 25 c ( 1 na over temperature). this results in a dc offset voltage developed across the source impedance. however, this dc offset effect can be compensated for by a combination of the differential input capability of the part and its system cali- bration mode. the dc input current on the ain2 input depends on the input voltage. for the nominal input voltage range of 10 v, the input current is 225 a typ. burnout current the ain1(+) input of the ad7712 contains a 4.5 a current source that can be turned on/off via the control register. this current source can be used in checking that a transducer has not burned out or gone open circuit before attempting to take mea- surements on that channel. if the current is turned on and is allowed to flow into the transducer and a measurement of the input voltage on the ain1 input is taken, it can indicate that the transducer is not functioning correctly. for normal operation, this burnout current is turned off by writing a 0 to the bo bit in the control register. bipolar/unipolar inputs the two analog inputs on the ad7712 can accept either unipo- lar or bipolar input voltage ranges. bipolar or unipolar options are chosen by programming the b/u bit of the control register. this programs both channels for either unipolar or bipolar operation. programming the part for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding. the data coding is binary for unipolar inputs and offset binary for bipolar inputs. the ain1 input channel is differential and, as a result, the voltage to which the unipolar and bipolar signals are referenced is the voltage on the ain1(e) input. for example, if ain1(e) is 1.25 v and the ad7712 is configured for unipolar operation with a gain of 1 and a v ref of 2.5 v, the input voltage range on the ain1(+) input is 1.25 v to 3.75 v. if ain1(e) is 1.25 v and the ad7712 is configured for bipolar mode with a gain of 1 and a v ref of 2.5 v, the analog input range on the ain1(+) input is e1.25 v to +3.75 v. for the ain2 input, the input signals are referenced to agnd. reference input/output the ad7712 contains a temperature compensated 2.5 v refer- ence, which has an initial tolerance of 1%. this reference voltage is provided at the ref out, pin and can be used as the reference voltage for the part by connecting the ref out pin to the ref in(+) pin. this ref out pin is a single-ended output, referenced to agnd, which is capable of providing up to 1 ma to an external load. in applications where ref out is connected directly to ref in(+), ref in(e) should be tied to agnd to provide the nominal 2.5 v reference for the ad7712. t he reference inputs of the ad7712, ref in(+) and ref in(e), provide a differential reference input capability. the common-mode range for these differential inputs is from v ss to av dd . the nominal differential voltage, v ref (ref in(+) e ref in(e)), is 2.5 v for specified operation, but the reference voltage can go to 5 v with no degradation in perfor- mance provided that the absolute value of ref in(+) and ref in(e) does not exceed its av dd and v ss limits and the v bias input voltage range limits are obeyed. the part is also functional with v ref voltages down to 1 v but with degraded performance as the output noise will, in terms of lsb size, be larger. ref in(+) must always be greater than ref in(e) for correct opera- tion of the ad7712. both reference inputs provide a high impedance, dynamic load similar to the ain1 analog inputs. the maximum dc input leakage current is 10 pa ( 1 na over temperature), and source resistance may result in gain errors on the part. the reference inputs look like the ain1 analog input (see figure 7). in this case, r int is 5 k typ and c int varies with gain. the input sample rate is f clk in /256 and does not vary with gain. for gains of 1 to 8, c int is 20 pf; for a gain of 16, it is 10 pf; for a gain of 32, it is 5 pf; for a gain of 64, it is 2.5 pf; and for a gain of 128, it is 1.25 pf. the digital filter of the ad7712 removes noise from the refer- ence input just as it does with the analog input, and the same limitations apply regarding lack of noise rejection at integer multiples of the sampling frequency. the output noise perfor- mance outlined in tables i and ii assumes a clean reference. if the reference noise in the bandwidth of interest is excessive, it can degrade the performance of the ad7712. using the on-chip reference as the reference source for the part (i.e., connecting ref out to ref in) results in somewhat degraded output noise performance from the ad7712 for portions of the noise table that are dominated by the device noise. the on-chip refer- ence noise effect is eliminated in ratiometric applications where the reference is used to provide its excitation voltage for the an alog front end. the connection scheme shown in figure 9 between the ref out and ref in pins of the ad7712 is recom mended when using the on-chip reference. recommended reference voltage sources for the ad7712 include the ad780 and ad680 2.5 v references. ref out ref in(+) ad7712 ref in(e) figure 9. ref out/ref in connection
rev. f ad7712 e17e v bias input the v bias input determines at what voltage the internal analog circuitry is biased. it essentially provides the return path for analog currents flowing in the modulator, and as such it should be driven from a low impedance point to minimize errors. for maximum internal headroom, the v bias voltage should be set halfway between av dd and v ss . the difference between av dd and (v bias + 0.85 v ref ) determines the amount of headroom the circuit has at the upper end, while the difference between v ss and (v bias e 0.85 v ref ) determines the amount of headroom the circuit has at the lower end. care should be taken in choosing a v bias voltage to ensure that it stays within prescribed limits. for single +5 v operation, the selected v bias voltage must ensure that v bias 0.85 v ref does not exceed av dd or v ss or that the v bias voltage itself is greater than v ss + 2.1 v and less than av dd e 2.1 v. for single +10 v operation or dual 5 v operation, the selected v bias voltage must ensure that v bias 0.85 v ref does not exceed av dd or v ss or that the v bias voltage itself is greater than v ss + 3 v or less than av dd e 3 v. for example, with av dd = +4.75 v, v ss = 0 v and v ref = +2.5 v, the allowable range for the v bias voltage is +2.125 v to +2.625 v. w ith av dd = +9.5 v, v ss = 0 v and v ref = +5 v, the range for v bias is +4.25 v to +5.25 v. with av dd = +4.75 v, v ss = e4.75 v, and v ref = +2.5 v, the v bias range is e2.625 v to +2.625 v. the v bias voltage does have an effect on the av dd power supply rejection performance of the ad7712. if the v bias voltage tracks the av dd supply, it improves the power supply rejection from the av dd supply line from 80 db to 95 db. using an external zener diode connected between the av dd line and v bias as the source for the v bias voltage gives the improvement in av dd power supply rejection performance. using the ad7712 system design considerations the ad7712 operates differently from successive approximation adcs or integrating adcs. since it samples the signal continu- ously, like a tracking adc, there is no need for a start convert command. the output register is updated at a rate determined by the first notch of the filter, and the output can be read at any time, either synchronously or asynchronously. clocking the ad7712 requires a master clock input, which may be an external ttl/cmos compatible clock signal applied to the mclk in pin with the mclk out pin left unconnected. alternatively, a crystal of the correct frequency can be connected between mclk in and mclk out, in which case the clock circuit will function as a crystal controlled oscillator. for lower clock frequencies, a ceramic resonator may be used instead of the crystal. for these lower frequency oscillators, external ca pacitors may be required on either the ceramic resonator or on the crystal. the input sampling frequency, the modulator sampling frequ ency, the e3 db frequency, the output update rate, and the calibration time are all directly related to the master clock frequency, f clk in. reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and will double the cali bration time. the current drawn from the dv dd power supply is also directly related to f clk in . reducing f clk in by a factor of 2 will halve the dv dd current but will not affect the current drawn from the av dd power supply. system synchronization if multiple ad7712s are operated from a common master clock, they can be synchronized to update their output registers simul- taneously. a falling edge on the sync ad2a ad2 sync tad2 t sync d dd iad2 d dd d dd ad2 t ad2 d dd t ad2t ad2i ad2 sync ad2ad2arc sync rcd dd sync a sadcfcadc tad2 t t ad2 a aad2 a i ad2 tad2 f t i 2
rev. f e18e ad7712 the ad7712 also provides the facility to write to the on-chip calibration registers, and, in this manner, the span and offset for the part can be adjusted by the user. the offset calibration regis- ter contains a value that is subtracted from all conversion results, while the full-scale calibration register contains a value that is multiplied by all conversion results. the offset calibra tion coefficient is subtracted from the result prior to the multiplication by the full-scale coefficient. in the first three modes outlined here, the drdy i drdy drdy t drdy sc i ainain bias ainain2 bias ain2 rf t t rf t d2ddi rf drdy t a f i ad2 sc sad2 s ains t i s d2d dt drdy a d2d da drdy i t a t d2ddt s arc sc s i ain sd2 ddt ain ain rf t ain t drdy i bc tad2 i rf t d2d d ad2 b i a d2d d ad2 f ti i
rev. f ad7712 e19e table vi. calibration truth table cal type md2, md1, md0 zero-scale cal full-scale cal sequence duration self-cal 0, 0, 1 shorted inputs v ref one-step 9 1/output rate system cal 0, 1, 0 ain e two-step 4 1/output rate system cal 0, 1, 1 e ain two-step 4 1/output rate system offset cal 1, 0, 0 ain v ref one-step 9 1/output rate background cal 1, 0, 1 shorted inputs v ref one-step 6 1/output rate span and offset limits whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. the range of input span in both the unipolar and bipolar modes for ain1 has a minimum value of 0.8 v ref /gain and a maxi- mum value of 2.1 v ref /gain. for ain2, both numbers are a factor of 4 higher. the amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. this offset range is limited by the requirement that the positive full-scale calibration limit is 1.05 v ref /gain for ain1. therefore, the offset range plus the span range cannot exceed 1.05 v ref / gain for ain1. if the span is at its minimum (0.8 v ref / gai n ), the maximum the offset can be is (0.25 v ref /gain) for ain1. for ain2, both ranges are multiplied by a factor of 4. in the bipolar mode, the system offset calibration range is again restricted by the span range. the span range of the converter in bipolar mode is equidistant around the voltage used for the zero-scale point, thus the offset range plus half the span range cannot exceed (1.05 v ref /gain) for ain1. if the span is set to 2 v ref /gain, the offset span cannot move more than (0.05 v ref /gain) before the endpoints of the transfer func- tion exceed the input overrange limits (1.05 v ref /gain) for ain1. if the span range is set to the minimum (0.4 v ref / gain), the maximum allowable offset range is (0.65 v ref / gain) for ain1. once again, for ain2, both ranges are multiplied by a factor of 4. power-up and calibration on power-up, the ad7712 performs an internal reset, which sets the contents of the control register to a known state. how- ever, to ensure correct calibration for the device, a calibration routine should be performed after power-up. the power dissipation and temperature drift of the ad7712 are low and no warm-up time is required before the initial calibra- tion is performed. however, if an external reference is being used, this reference must have stabilized before calibration is initiated. drift considerations the ad7712 uses chopper stabilization techniques to minimize input offset drift. charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. the dc input leakage cur- rent is essentially independent of the selected gain. gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. it is not affected by leakage currents. measurement errors due to offset drift or gain drift can be elimi- nated at any time by recalibrating the converter or by operating the part in the background calibration mode. using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. integral and differential linearity errors are not significantly affected by temperature changes. power supplies and grounding since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. v bias provides the return path for most of the analog currents flowing in the analog modulator. as a result, the v bias input should be driven from a low impedance to minimize er rors due to charging/discharging impedances on this line. when the internal reference is used as the reference source for the part, agnd is the ground return for this reference voltage. the analog and digital supplies to the ad7712 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. the digital supply (dv dd ) must not exceed the analog positive supply (av dd ) by more than 0.3 v in normal operation. if sepa- rate analog and digital supplies are used, the decoupling scheme shown in figure 10 is recommended. in systems where av dd = 5 v and dv dd = 5 v, it is recommended that av dd and dv dd are driven from the same 5 v supply, although each supply should be decoupled separately as shown in figure 10. it is preferable that the common supply is the system?s analog 5 v supply. it is also important that power is applied to the ad7712 before signals at ref in, ain, or the logic input pins in order to avoid excessive current. if separate supplies are used for the ad7712 and the system digital circuitry, then the ad7712 should be powered up first. if it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs. ad7712 0.1 f 0.1 f 10 f analog supply digital 5v supply av dd dv dd figure 10. recommended decoupling scheme
rev. f e20e ad7712 digital interface the ad7712?s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers, and digital signal processors. a serial read to the ad7712 can access data from the output register, the control register, or the calibration registers. a serial write to the ad7712 can write data to the control register or the calibration registers. two different modes of operation are available, optimized for different types of interfaces where the ad7712 can act either as master in the system (it provides the serial clock) or as slave (an external serial clock can be provided to the ad7712). these two modes, labeled self-clocking mode and external clocking mode, are discussed in detail in the following sections. self-clocking mode the ad7712 is configured for its self-clocking mode by tying the mode pin high. in this mode, the ad7712 provides the serial clock signal used for the transfer of data to and from the ad7712. this self-clocking mode can be used with processors that allow an external device to clock their serial port, including most digital signal processors and microcontrollers such as the 68hc11 and 68hc05. it also allows easy interfacing to serial parallel conversion circuits in systems with parallel data com- munication, allowing interfacing to 74xx299 universal shift registers without any additional decoding. in the case of shift registers, the serial clock line should have a pull-down resistor instead of the pull-up resistor shown in figures 11 and 12. read operation data can be read from the output register, the control register, or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibra- tion registers. this a0 signal must remain valid for the duration of the serial read operation. with a0 high, data is accessed from either the output register or from the calibration registers. with a0 low, data is accessed from the control register. the function of the drdy drdy i 2i drdy t drdy a i drdy drdy d drdy irfs drdy drdy fad2 t ad2a drdy d a 2 fad2f sc drdy rfs rfs ad2sb a tsc sbsb scc sc drdy drdy scsdata sb sdata sc trstat rfs i ai drdy sb sb 2 f scdr
rev. f ad7712 e21e write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy drdy a 2 f2ad2a ta t tfs sc tad2 scd ad2scsb scsb ad2s scsct f2sc c tad2 discad2 sct ccc c r a a ta a a t drdy drdy i 2i drdy t drdy a i drdy drdy d drdy irfs drdy drdy f ad2f ad2 f ad2b ad2 r drdy d a 2 sdata sc tfs i ai sb sb f2 scccr
rev. f e22e ad7712 figure 13a shows a read operation from the ad7712 where rfs drdy rfs t sc rfs sb a t scsb drdy t drdy f rfs t ff rfs rfs sc rfs sdata drdy ad2 rfs d sc rfs bitn rfs rfs sdata drdy sdata f rfs i sci sdata sb sb trstat ai drdy 2 2 22 2 2 2 2 2 2 2 f cdr trstat sb bitn bitn sdata sci rfs i ai drdy 2 22 2 2 2 2 2 2 f cdr rfs rr
rev. f ad7712 e23e write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy drdy a 2 fad2 tfs a ta a tad2 sc dad2 scsb scsbad2 f ad2 tfs t ff tfs dad2 sc tfs sca tfs ad2 sc scsbad2 sci sdatai tfs i ai sb sb 2 2 2 f cccr sci sdatai tfs i ai sb bitn bitn 2 2 2 f cccr tfs r
rev. f e24e ad7712 simplifying the external clocking mode interface in many applications, the user may not require the facility of writing to the on-chip calibration registers. in this case, the serial interface to the ad7712 in external clocking mode can be simplified by connecting the tfs a ad2ft a tfs a rfs i ad2 sdata sc tfs a frintr facins rfs f si tfs tfs rfs rfs tfs icrctricrrcssrintrfacin tad2 f ad2f ad2 f2 tf ad2i drdy d drdy drdy r 2 a drdy ta rfs t t sbsb tad2sb n ys brin rfs rrs rdrfbits brin rfs i drdy cnfirand initiai c sriart drdy brin rfs tfs i rad sriabffr start f fcr ad2 tf2 ad2t s t t sbsbtad2sb i
rev. f ad7712 e25e reverse order of bits start write data from accumulator to serial buffer bring tfs and a0 low load data from address to accumulator configure and initialize c/ p serial port bring rfs , tfs and a0 high bring tfs and a0 high end 3 figure 17. flowchart for single write operation to the ad7712 ad7712 to 8051 interface figure 18 shows an interface between the ad7712 and the 8xc51 microcontroller. the ad7712 is configured for its external clocking mode, while the 8xc51 is configured in its mode 0 serial interface mode. the drdy ad2 2c drdy ct drdy intc 2 d dd c ad2 sdata a rfs tfs d drdy sync sc fad2ci tiic 2ad2tiii ad2tcsb ad2sb sad2 sbc sbt ad2 tii ccrad2 scnb cd ib dai stb s rfs stb s tfs stb sa r snbbr ar r sab b r 2 drdy ait n a r anar ab drdy rad ir sait rad cr b rfs cr crf brad trif s rad asbf rb rca rd bc rb rcabcrcab2c rcabcrcabc rcabcrcabc rcabc ab ra d incr i dcr dbc ar nd ait fnb nd stb b rfs fin sfin
rev. f e26e ad7712 table viii. 8xc51 code for writing to the ad7712 mov scon,#00000000b; configure 8051 for mode 0 operation & enable serial recep tion mov ie,#10010000b; enable transmit interrupt mov ip,#00010000b; prioritize the transmit interrupt setb 91h; bring tfs stb b rfs r snbb r sarab a ca sbfa is ait ait i intrtin n is ar ra fin ifin dcr drbc ar ba incr ia rca rdfsbf sbf bcrcabcrca b2crcabcrca bcrcabcrca bcrcabcab cr ba cr b tfs sbfa s rti rs fin stb s tfs stb sa rti ris ad2ci fad2 ctad2 si ct drdy ad2c2 c drdy ct drdy irq c tcsi isr d csi is tcc ca ad2 c ad2 sdata sc a rfs tfs c is sc c c2 d c drdy sync c si ss d dd d dd f ad2ci
rev. f ad7712 e27e clock generation serial interface output register charge-balancing a/d converter auto-zeroed e modulator digital filter ad7712 agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(e) ref in (e) ref in (+) sync 4.5 a a = 1 e 128 drdy tfs rfs ref out 2.5v reference voltage attenuation ain2 standby control register v ss 500 pga m u x av dd av dd dv dd analog +5v supply v bias 4e20ma loop figure 20. 4e20 ma loop measurement using the ad7712 applications 4e20 ma loop the ad7712?s high level input can be used to measure the current in 4e20 ma loop applications as shown in figure 20. in this case, the system calibration capabilities of the ad7712 can be used to remove the offset caused by the 4 ma flowing through the 500 resistor. the ad7712 can handle an input span as low as 3.2 v ref (= 8 v with a v ref of 2.5 v) even though the nominal input voltage range for the input is 10 v. therefore, the full span of the a/d converter can be used for measuring the current between 4 ma and 20 ma. 24-lead standard small outline package [soic] wide body (rw-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) outline dimensions
rev. f c01177e0e3/04(f) e28e ad7712 revision history location page 3/04?data sheet changed from rev. e to rev. f. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 deleted ad7712 to adsp-2105 interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 changes to ad7712 to 68hc11 interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 outline dimensions 24-lead ceramic dual in-line package [cerdip] (q-24) dimensions shown in inches and (millimeters) 24 112 13 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 24-lead plastic dual in-line package [pdip] (n-24) dimensions shown in inches and (millimeters) 24 1 12 13 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095ag

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